Technical Field
The present invention relates generally to integrated circuits and, in particular, to a resonant virtual supply booster for synchronous logic circuits and other circuits with the use of an on-chip integrated magnetic inductor.
Description of the Related Art
Static and Dynamic logic circuits are used in memories and logic devices to provide high frequency operation with a minimum of die area for performing logical operations and providing storage functionality. Both synchronous static and dynamic logic circuits have controlled evaluation times in that the operation of the circuit before and during a time at which an output value of the logic block evaluates or changes state is determined from the input logic or a storage cell value.
Groups of logic circuits, which are sometimes referred to as “macros”, have been power-managed in existing circuits to reduce power consumption, except during certain intervals of time in which power supply current is drawn to provide a read or a write of a storage cell value, or the determination of a logic combination. For example, a dynamic logic circuit may draw no current, or have very low leakage current levels, except when a signal node is pre-charged with a voltage and then selectively discharged to produce the combinatorial output or storage cell value. A static logic circuit or storage cell only draws significant current when a state change occurs.
Logic circuits have been implemented that include virtual power supply nodes that can be disabled or set to a reduced voltage when the logic circuits are not evaluating, or multiple power supplies can be used to supply higher voltages to critical circuits. In some implementations, circuits have been provided that boost the power supply voltage supplied to the logic circuits during the evaluation phase to reduce the static power supply voltage by including a boost transistor. Such boosting reduces overall power supply voltage requirements. However, the energy expended in changing the voltage of the virtual power supply node voltage offsets any advantage gained, since the virtual power supply nodes typically have large shunt capacitance due to the large numbers of devices that are connected to the virtual power supply nodes.
It would therefore be desirable to provide a virtual power supply circuit for synchronous logic and other logic having a predictable evaluate time that provides for reductions in overall power supply voltage and energy consumption.